This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A typical computer communicates with a great many input output (“I/O”) devices during its normal operation. One method of organizing and controlling this communication involves implementing interrupts. In an interrupt-based computer system, when one of the I/O devices requires attention from the computer's CPU, it generates an interrupt. When the CPU receives the interrupt, it typically stops its current task, sends an instruction to the I/O device to stop asserting the interrupt, and enters an interrupt mode to process the interrupt. Any interrupt generated by one of the I/O devices after the CPU has issued the instruction to de-assert the interrupt may be referred to as a “spurious interrupt”. After completing the interrupt-related processing tasks, the CPU re-arms the device, then typically exits from the interrupt mode and sends an End of Interrupt (“EOI”) signal to the interrupt controller. The EOI signal indicates that the CPU 12 has finished processing the interrupt and that the CPU is available to process another interrupt. If the CPU receives a spurious interrupt after this point, it may produce a “spurious interrupt error.”
In recent years, the number of spurious interrupts errors generated by typical computer systems has increased dramatically because increases in CPU speed have outpaced increases in I/O device speed and chipset speed. Since most of these spurious interrupt errors are a natural byproduct of unavoidable propagation delays within the computer system in combination with the previously mentioned widening gap in system component speeds, they are not a real cause for concern. Accordingly, there is often no need to generate an error. Conventional methods of suppressing spurious interrupts involve inserting a fixed delay before the processor generates the EOI signal. While this method can be effective in suppressing spurious interrupts, it can degrade system performance more than necessary by introducing often unnecessarily lengthy delays in interrupt processing.